when the source and drain of a n-mos is shorted results capacitor or diode

Similar threads

• B

  Port is not connected when using top module

  • Started by Boris.b
  • Jan 22, 2024
  • Replies: 3

  PLD, SPLD, GAL, CPLD, FPGA Design
• K

  What's the difference between RAM and ROM with a coe files in Xilinx FPGA?

  • Started by kevinwang65
  • Mar 11, 2024
  • Replies: 13

  PLD, SPLD, GAL, CPLD, FPGA Design
• M

  [SOLVED] VHDL Based N-point FFT with fixed point package really slow, suggestions or improvements?

  • Started by mhmert
  • Aug 17, 2023
  • Replies: 13

  PLD, SPLD, GAL, CPLD, FPGA Design
• M

  How to instantiate another vhd file inside testbench, where the testbench is used for opening files

  • Started by metamisers
  • Jan 6, 2024
  • Replies: 6

  PLD, SPLD, GAL, CPLD, FPGA Design
• Z

  What does this error mean when trying to Optimize a PLD design?

  • Started by Zag4cpld
  • Jun 5, 2023
  • Replies: 2

  PLD, SPLD, GAL, CPLD, FPGA Design