when clock and reset are on the same clock edge .

[kil]

hi all ,

what happens when clock and reset are on the same edge of clock(when both are either +ve or -ve edge) .

what happens when they are on different edge of clock(clock on +ve edge and reset on -ve edge ):?:

:idea:what the advantages and disadvantages of having synchronous reset and asynchronous reset.

thanks in advance

kil

 

[tarkyss]

I think you had better check the circuit structure of the flip-fliop you used

 

[sesl33]

hi all ,

what happens when clock and reset are on the same edge of clock(when both are either +ve or -ve edge) .

what happens when they are on different edge of clock(clock on +ve edge and reset on -ve edge ):?:

:idea:what the advantages and disadvantages of having synchronous reset and asynchronous reset.

thanks in advance

kil

It really depends on your circuit. I assume that you are talking about a flip-flop here.
For Synchronous reset:

Now, if you use synchronous reset, there is a setup time that is required to be satisfied before the circuit is reset. Typically, if reset and clk is on the same edge, the circuit will reset on the next clk cycle(for synchronous reset). If they are on the different edge, then, on the next rising edge of the clk, reset will be activated.

PS: I assume that your flip-flop is positive triggered and reset is also active High.

For Asynchronous reset:

Typically, reset has priority over data. Hence, as long as your reset triggers, the circuit should be reset -- regardless of the clk.

 

[kil]

thanks guys

actually when we donot menction in our coding by default it will take as synchronous with respect to clk ( always @(posedge clk) ) like this .

:!: if we want to make it asynchronous we should menction it in always block right
ie ( always @( posedge clk , negedge reset) like this .

can u give me any pdf or any reference link on this .


kil:idea:

 

[Kronos!!]

I dont know if this is what your question was about but ...

1. If the flop has an async reset pin (depends on circuit of flop) then connecting your reset signal to this pin will ensure reset of flop even if the clock is stopped at the time of reset. Also the duration of reset signal (pulse width) will be independent of clock and only depends on minimum pulse width supported by the flop.

2. Even with async reset you need to ensure that recovery and removal checks are satisfied i.e. clock and reset edges are not too close together.

3. (posedge of clock and negedge of reset) or (negedge of clock and negedge of reset) of any other combination only depends on flop circuit (active low or active high reset, positive edge triggered or negative edge triggered clock etc). In every case recovery and removal need to be satisfied.

4. For synch reset the flop's reset pin is not used. In effect the flop is just capturing data which is held to stable 0 or 1 by the reset signal. Normal setup/hold checks must be satisfied.

 

[nitin_ndg]

Do design sync reset in VHDL write

Presess(clk)
begin
if clk'event and clk='1' then
if reset='1' then
D<='0';
else
D<=Q;
end if;
end if;
end process;
-----------------------------------------------
Do design Async reset in VHDL write

Presess(clk,reset)
begin
if reset='1' then
D<='0';
elsif clk'event and clk='1' then
D<=Q;
end if;
end process;

IMP: see the difference in process sensitivity list

 

[lubee]

if your reset is asynchronous, you must pay your high attentions to "recovery" and "removal" check.