Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

When and why are gated clocks used?

Status
Not open for further replies.

phutanesv

Full Member level 3
Joined
Apr 26, 2007
Messages
151
Helped
19
Reputation
38
Reaction score
7
Trophy points
1,298
Activity points
2,233
Der dudes,

I am in small confusion, i know about gated clocks

if its used power dissipation will be less, but

glicth , timing issues, slew, are some of diffculties.

But so far i know gated clock must be avoided

So my confusion do we use Gated clock or not.?

phutane
 

omara007

Advanced Member level 4
Joined
Jan 6, 2003
Messages
1,238
Helped
50
Reputation
102
Reaction score
16
Trophy points
1,318
Location
Cairo/Egypt
Activity points
9,747
About Gated clocks

Gated clocks are used under some constraints .. usually circuits used for that are technology dependant and can be infered during synthesis if your RTL was originally coded in a specific style/way in order to do that ..
 

research235

Full Member level 6
Joined
Mar 15, 2006
Messages
331
Helped
24
Reputation
48
Reaction score
6
Trophy points
1,298
Activity points
3,100
About Gated clocks

in low power design we use clock gating. so where power dessipation an important perfomance aspect. we use clock gating
 

megastar007

Member level 4
Joined
Feb 20, 2007
Messages
71
Helped
10
Reputation
20
Reaction score
5
Trophy points
1,288
Location
Munich
Activity points
1,662
Re: About Gated clocks

we will be using special lib cells for clock gating cell with this their is no problem in glitches etc
 

qcioo

Newbie level 2
Joined
Aug 27, 2007
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,291
About Gated clocks

The question is if You have to use it or not. Generally clock gating is not always simple and may couze problems like one You described. But in moder circuits power comsumption is very important not only in battery using things but in microprocesors also. So better get used to clock gating and other poser saving techniques like changes Vt or sleep modes.
 

Fom

Advanced Member level 2
Joined
Mar 10, 2004
Messages
633
Helped
84
Reputation
168
Reaction score
31
Trophy points
1,308
Location
Taiwan
Activity points
4,451
Re: About Gated clocks

Gated clock is useful not only for reducing power consumption.
The digital blocks with gated clock generate much less switching noise.
If your application used high resolution ADC you should care about that also.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top