What's Wrong with this VHDL code ??? or maybe with ISE !

[hm_fa_da]

Hi all ,

I don't know what's wrong with this code ! i am really getting confused ...

when i run it in ISE webedition v9.1 , it gives fata error !!! but not in ISE V8.1 !!!
in V9.1 , when i delete + 1 from line30 , it doesn't give Fatal Error ,

However my problem is not that ! :!: ,my problem is :
in warning section it says that :
WARNING:Xst:646 - Signal <ram0> is assigned but never used.
WARNING:Xst:646 - Signal <result2> is assigned but never used.

BUT i have used them in code , in loop , line57 and in line62 ...
in this case that ISE says , in fact it is not synthesizing what i want !!!
the code contains these parts : getting data and saving to ram ,
moving from ram to do ( ram too ) , and moving from do to outputs ...


i'll be thankful you help me

here is the code :


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity test is

port (
clk,frame,cs,e,lnumber : in std_logic ;
data : in std_logic_vector ( 7 downto 0 ) ;
refs : out std_logic_vector ( 112 downto 1 )) ;
end test;

architecture Behavioral of test is

type ram_all is array ( 224 downto 1 ) of integer range 0 to 255 ;
type outreg is array ( 112 downto 1 ) of integer range 0 to 255 ;

signal ram0 : ram_all ;
signal address1 : integer range 1 to 224 := 1 ;
signal result : integer range 1 to 224 :=1 ;
signal result2 : integer range 1 to 224 :=1 ;
signal mk : integer range 0 to 10 ;
signal do : outreg ;
signal cnt : integer range 0 to 10 := 0 ;
signal cnt2 : integer range 0 to 255 := 0 ;

begin
mk <= conv_integer(frame) ; --******line30
result <= address1 * mk ;
result2 <= conv_integer(lnumber) * 112 * (conv_integer(not(frame))) ;


process(clk,e,cs,result,result2)
variable rez,rez2 : integer range 1 to 224 := 1 ;
begin
rez := result ;
rez2 := result2 ;
if ( clk'event and clk = '1' ) then
if ( e='1' and cs = '1' ) then
if address1 = 224 then
address1 <= 1 ;
else
address1 <= address1 + 1 ;
end if ;
ram0(rez) <= conv_integer(data) ;
end if ;

cnt <= cnt + 1 ;
if cnt = 10 then
cnt <= 0 ;
cnt2 <= cnt2 + 1 ;

if cnt2 = 255 then -- load to do(i)
cnt2 <= 0 ;
s1: for i in 1 to 112 loop --******line57
do(i) <= ram0( rez2 + i );
end loop ;
end if ;

s2: for i in 1 to 112 loop --******line62
do(i) <= do(i) - 1 ;
if do(i) = 0 then
refs(i) <= '1' ; -- turn off
else
refs(i) <= '0' ; -- turn on
end if ;
end loop ;
end if ;
end if ;
end process ;

end behavioral ;

 

[bis_]

However my problem is not that ! ,my problem is :
in warning section it says that :
WARNING:Xst:646 - Signal <ram0> is assigned but never used.
WARNING:Xst:646 - Signal <result2> is assigned but never used.

BUT i have used them in code , in loop , line57 and in line62 ...
in this case that ISE says , in fact it is not synthesizing what i want !!!
the code contains these parts : getting data and saving to ram ,
moving from ram to do ( ram too ) , and moving from do to outputs ...

It is possible that, after all synthesis and optimizations, real usage of this resourses are "none" (due to cutting real connection of this resources to input/output signals of the module by commenting some lines).


bis

 

[avimit]

Dear hm_fa_da

s1: for i in 1 to 112 loop --******line57
do(i) <= ram0( rez2 + i );
end loop ;

You are not allowed to use signal assignments inside VHDL loops, unless you exactly know what you are doing, and on this occasion, you have got it wrong.
Just use 'variables' at the LHS of a assignments, and after loop finishes, transfer those variables into signals if you want to. Since signal assignment happens in next delta cycle, and loops are meant to be finished in the current delta cycle. so any signal assigned inside the loop, would effectively be 'unassigned' or 'unconnected' and that is why ISE says that you haven't made use of ram0 or result2(rez2)

If you believe me, most of the time its you not the tool . have fun.

kr,
Avi
http://www.vlsiip.com

 

[hm_fa_da]

Thanks too much dear avimit ,

i changed it and get true results ,
thanks again ,

but what about fatal error wich occurs in ISE9.1 in line30 ?
when i delete +1 from the line , then no Error , is it problem with ISE V9.1 software ? ( it doesn't occur in V8.1 ! )

Thanks & Best Regards.

 

[avimit]

Hi,
I cannot understand wot do you mean by '+1' , cut+paste the code and I will see. But I am quite sure it has to do with the 'range' you have set. May be doing a +1 somewhere(as you say), puts some signal into the range (1 to 224) you have defined, and not doing so puts some signal = 0 , which is out of range (1 to 224), and hence the error.
The thing is, you need to simulate the code, before putting it to FPGA, and your life will be far better.
Kr,
Avi
http://www.vlsiip.com

 

[hm_fa_da]

sorry , the code which i had problem with it was :

mk <= conv_integer(frame) + 1 ; --******line30

Dear Avimit , again you helped me , the range for result wasn't true , when i changed it , it worked .

Thanks Again .