what's wrong with this verilog code

Status
Not open for further replies.
M

MRFGUY

Full Member level 1
Joined
Sep 16, 2003
Messages
98
Helped
9
Reputation
18
Reaction score
3
Trophy points
1,288
Activity points
1,049
latch verilog code

In my simple verilog code, I saw some warnings. I still don't know how to clear.
And seg output is always at the default.
I used Xilinx.

Somebody can help me.

My code

warnings:
 

7-seg led verilog

You have defined "count" as a one bit signal. You should define it as follows:

reg [3:0] count OR (integer count!)

By the way, I recommend you to write your code in a standard style.

Define sequential signals as Present_state & Next_state categories.

always (YOUR_signals)
begin

Specifiy your Next_state signals in a combinational circuit
I mean: Next_state = Function (Present_state and other signals)

end

always @(negedge clk)
begin

Apply Next_state signals to related Present_state signals
I mean: Present_state <= Next_state;

end


RGDS
KH
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…