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what's wrong with this verilog code

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MRFGUY

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latch verilog code

In my simple verilog code, I saw some warnings. I still don't know how to clear.
And seg output is always at the default.
I used Xilinx.

Somebody can help me.

My code
module prj12(A, B, C, D, seg, clk, y);

// Whenever B.eqn is 1 led is on and it is count
// and display on 7 seg disp. Counting is done between 0 and 15 (4 bits)

input A, B, C, D, clk; // input taken from 7493
output [6:0] seg; // 7-seg disp
output y; // led
reg [6:0] seg = 0;
reg count;
reg y;
always @(negedge clk)
begin

y= (A&~D&B)|(B&C);

if (A&&B&&C&&D) count = 0; // count between 0 and 15
else if(y==1) count=count+1;

case (count)
0: seg = 7'b1111110;
1: seg = 7'b0110000;
2: seg = 7'b1101101;
3: seg = 7'b1111001;
4: seg = 7'b0110011;
5: seg = 7'b1011011;
6: seg = 7'b1011111;
7: seg = 7'b1110000;
8: seg = 7'b1111111;
9: seg = 7'b1110011;
10: seg = 7'b1110111;
11: seg = 7'b1111111;
12: seg = 7'b1001110;
13: seg = 7'b0111101;
14: seg = 7'b1001111;
15:seg = 7'b1000111;
default : seg = 7'b1010101;
endcase
end
endmodule

warnings:
WARNING:Xst:1293 - FF/Latch <seg_4> has a constant value of 1 in block <prj12>.
WARNING:Xst:1293 - FF/Latch <seg_5> has a constant value of 1 in block <prj12>.
WARNING:Xst:1293 - FF/Latch <seg_0> has a constant value of 0 in block <prj12>.
Register <seg_1> equivalent to <seg_6> has been removed
 

khorram

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7-seg led verilog

You have defined "count" as a one bit signal. You should define it as follows:

reg [3:0] count OR (integer count!)

By the way, I recommend you to write your code in a standard style.

Define sequential signals as Present_state & Next_state categories.

always (YOUR_signals)
begin

Specifiy your Next_state signals in a combinational circuit
I mean: Next_state = Function (Present_state and other signals)

end

always @(negedge clk)
begin

Apply Next_state signals to related Present_state signals
I mean: Present_state <= Next_state;

end


RGDS
KH
 

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