what's wrong with this program

[ektaagrawal12]

this program is for processing element of systolic array for 1-D type IV DCT. actually, i have a block diagram of it n i want to code it in VHDL. i have improved program my program but still there are lots of errors in this. plz, help me in this regard.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--use ieee.numeric_std.all;


-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
-- GENERIC(tprop : delay := 8 ns;
--tsu : delay := 2 ns);
entity node is
Port ( xe1 : in std_logic;
--d : IN std_logic;
clock : in std_logic;
-- Q, Qbar : --STD_LOGIC;
xe2 : in std_logic;
c : in std_logic;
y1 : in std_logic;
y2 : in std_logic;
-- tc : in bit;
-- tc1 : in std_logic;
-- tc2 : in std_logic;
xi1 : inout std_logic;
xi2 : inout std_logic;
xi11 : out std_logic;
xi22 : out std_logic;
xe11 : out std_logic;
xe22 : out std_logic;
c1 : out std_logic;
y22 : out std_logic;
y11 : out std_logic);
-- tcc : out bit);
end node;


architecture Behavioral of node is
signal tc,tcc,tc1,tc2: std_logic;
begin
process(tc,tcc,tc1,tc2)
begin
xe11<=xe1;
xe22<=xe2;
tcc<=tc;
if (tc='1') then
xi11<=xe1;
xi22<=xe2;
if (tc1='1') then
y11<=y1-xe1*c;
else
y11<=y1+xe1*c;
end if;
if (tc2='1') then
y22<=y2-xe2*c;
else
y22<=y2+xe2*c;
end if;
--else (tc='0')
else
--xi11<=xi1;
--xi22<=xi2;

process (clock)
if (clock’event and clock = ‘1’) then
xi1<=xi1;--output <= data;
xi2<=xi2;
end if;
if (clock’event and clock = ‘1’) then
xi1<=xi1;--output <= data;
xi2<=xi2;
end if;
end process;
xi11<=xi1;
xi22<=xi2;
if (tc1='1')then
y11<=y1-xi1*c;
else
y11<=y1+xi1*c;
end if;
if (tc2='1') then
y22<=y2-xi2*c;
else
y22<=y2+xi2*c;
end if;
--end if;
end process;

end Behavioral;

 

[falloutmx]

check your code again.
as you didn't declare 'clock',there has many more error.

 

[permute]

indeed. the error listed is that there is no operator defined for "bit" * "bit".

but looking at the rest of the code, I'm guessing you'll have an easier time reading up on VHDL and hardware design, then rewriting it.

 

[vipinlal]

some points about the code:

1)Use either

IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

(OR)
use ieee.numeric_std.all;

dont use both.

2)Since all your signals/variables are 1 bit in size use the "std_logic" type instead of "bit". I think if you use "std_logic" then it is easier to find multiple source signal errors.

3)Since you are doing bit multiplication remove the multiplication sign. Use AND gate instead.
Because x*y = x and y; if x,y are bits.

4)And if you want you can have a vector of bits defined.Use "std_logic_vector" / "unsigned" / "signed" for that.This will make the program less complicated and easier to understand.

By the way what does the above program do?

--vipin
https://vhdlguru.blogspot.com/

 

[ektaagrawal12]

this program is for peocessing element of systolic array for 1-d DCT type-IV. i have a block diagram of it and i want to code it in VHDL. still there are errors in it.

plz, help me in this regardd.
thanx.


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--use ieee.numeric_std.all;


-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
-- GENERIC(tprop : delay := 8 ns;
--tsu : delay := 2 ns);
entity node is
Port ( xe1 : in std_logic;
--d : IN std_logic;
clock : in std_logic;
-- Q, Qbar : --STD_LOGIC;
xe2 : in std_logic;
c : in std_logic;
y1 : in std_logic;
y2 : in std_logic;
-- tc : in bit;
-- tc1 : in std_logic;
-- tc2 : in std_logic;
xi1 : inout std_logic;
xi2 : inout std_logic;
xi11 : out std_logic;
xi22 : out std_logic;
xe11 : out std_logic;
xe22 : out std_logic;
c1 : out std_logic;
y22 : out std_logic;
y11 : out std_logic);
-- tcc : out bit);
end node;


architecture Behavioral of node is
signal tc,tcc,tc1,tc2: std_logic;
begin
process(tc,tcc,tc1,tc2)
begin
xe11<=xe1;
xe22<=xe2;
tcc<=tc;
if (tc='1') then
xi11<=xe1;
xi22<=xe2;
if (tc1='1') then
y11<=y1-xe1*c;
else
y11<=y1+xe1*c;
end if;
if (tc2='1') then
y22<=y2-xe2*c;
else
y22<=y2+xe2*c;
end if;
--else (tc='0')
else
--xi11<=xi1;
--xi22<=xi2;

--process (clock)
--if (clock’event and clock = ‘1’) then
--xi1<=xi1;--output <= data;
--xi2<=xi2;
--end if;
--if (clock’event and clock = ‘1’) then
--xi1<=xi1;--output <= data;
--xi2<=xi2;
--end if;
--end process;
xi11<=xi1;
xi22<=xi2;
if (tc1='1')then
y11<=y1-xi1*c;
else
y11<=y1+xi1*c;
end if;
if (tc2='1') then
y22<=y2-xi2*c;
else
y22<=y2+xi2*c;
end if;
end if;
end process;

end Behavioral;

 

[lucbra]

Hello,

Writing code is one thing, debugging is another, asking for help is a 3th.

Just throwing your code here, and hoping someone will pick it up a debug it for you is (IMHO) pretty rude.

Maybe you can start with telling the community which errors you are facing, what you allready tried, and maybe try to format the code (use the "Code" tags) so that is is easy to read (some comments can help).

If you follow these simple rules, you will get help pretty soon.

To give you an example: you will need to have a look at

signal tc : std_logic;

if (tc = '1') then ...

- this signal has never been assigned a value, and thus will cause certainly a warning. And on top it's in the sensitivity list of a process ...

Regards