What's wrong with the verilog code?

[corgan]

I would like to design a first order IIR high filter with equeation y[n] = x[n] - x[n-1] + a * y[n-1]
I wrote the following verilog code, but the result is not correct . Can any one tell me why?


input wire signed [15:0] Xn,
output reg signed [16:0] Yn,

parameter a = 0.9;

reg signed [15:0] Xn-1;
wire signed [16:0] diff = Xn-Xn-1;

always @(posedge clk or negedge reset) begin
if (reset) begin
Xn-1 <= 0;
Yn <= 0;
end
else begin
Xn-1 <= Xn;
Yn <= diff + a*Yn;
end
end

 

[CDRCDR]

You need to update the diff = xn-xn-1 in the process instead of at the declaration.

 

[corgan]

You need to update the diff = xn-xn-1 in the process instead of at the declaration.

Xn-1 is updated every cycle. diff is updated every cycle too.
It's not necessary to put diff in the always block.