So after the state 1010, the next rising clock will change q0 to 1 which subsequently changes q1 to 0. At this point, the output is 1001. When this happens, your NAND gate will set the output to 1110, as you had expected. The problem is that this means that q2 and q3 both see a rising edge (from 1001 -> 1110) and both are toggled again. This leaves the output at 0010. You should see this in your timing diagram if you zoom into the area right after the clock transistion of the 1010 edge.