what's wrong in my netlist(PLL) ? Please help

[joong338]

This is Pll netlist. But output of cpout is wrong. please find what wrong is.

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***full***
.lib 'c:\pll\hl18g-s3.5s.lib' tt_tn
.OPTION node post list
.global vdd gnd
.op
vdd vdd gnd 1.8v
vref  fref  gnd pulse(0 1.8v 0u 1p 1p 32n 64n)
.ic V(cpout)=0v
******************PFD*****************
*****DF****
Mb1 b3 b2 vdd vdd PCH_tn l=0.18u w=5u
Mb2 b4 fref b3 vdd pCH_tn l=0.18u w=5u
Mb3 b4 b2 gnd gnd nCH_tn l=0.18u w=2u
Mb4 b5 b4 vdd vdd pCH_tn l=0.18u w=5u
Mb5 b5 fref b6 gnd nCH_tn l=0.18u w=2u 
Mb6 b6 b4 gnd gnd nCH_tn l=0.18u w=2u
*****DF****(11-16)
Mb11 b15 b2 vdd vdd pCH_tn l=0.18u w=5u
Mb12 b14 fdiv b15 vdd pCH_tn l=0.18u w=5u
Mb13 b14 b2 gnd gnd nCH_tn l=0.18u w=2u
Mb14 b9 b14 vdd vdd pCH_tn l=0.18u w=5u
Mb15 b9 fdiv b11 gnd nCH_tn l=0.18u w=2u
Mb16 b11 b14 gnd gnd nCH_tn l=0.18u w=2u
***NOR***(7-9)
Mb7 b8 b5 vdd vdd pCH_tn l=0.18u w=10u
Mb8 b2 b9 b8 vdd pCH_tn l=0.18u w=10u
Mb9 b2 b9 gnd gnd nCH_tn l=0.18u w=2u
Mb10 b2 b5 gnd gnd nCH_tn l=0.18u w=2u
*****Inver1****
Mb17 up b5 vdd vdd pCH_tn l=0.18u w=5u
Mb18 up b5 gnd gnd nCH_tn l=0.18u w=2u
****INVER2****
Mb19 dn b9 vdd vdd pCH_tn l=0.18u w=5u
Mb20 dn b9 gnd gnd nCH_tn l=0.18u w=2u
********************CP*****************
**current mirror     *** if node vdd=1 gnd=0 proceed, also if pmos body=vdd 1, if nmos body=gnd 0
Mc1 c3 gnd vdd vdd pch_tn l=1u w=10u
Mc2 c5 c5 c3 vdd pch_tn l=1u w=10u
Mc3 c4 gnd vdd vdd pch_tn l=0.5u w=5u
Mc4 c6 c5 c4 vdd pch_tn l=0.4u w=10u
Mc5 c5 vdd gnd gnd nch_tn l=0.5u w=0.4u
Mc6 c6 c6 c7 gnd nch_tn l=0.8u w=6.3u
Mc7 c7 vdd gnd gnd nch_tn l=0.4u w=8u
**UpSwitch
Mc8 c9 upb vdd vdd pch_tn l=0.3u w=10u
Mc9 cpout c5 c9 vdd pch_tn l=0.4u w=23u
**DownSwitch
Mc10 cpout c6 c8 gnd nch_tn l=0.4u w=15u
Mc11 c8 dn gnd gnd nch_tn l=1u w=14u
**NOT**
Mc13 upb up vdd vdd pCH_tn l=0.18u w=5u
Mc14 upb up gnd gnd nCH_tn l=0.18u w=2u
clpf cpout gnd 50p
rlpf cpout c10 1k
clpf1 c10 gnd 500p
***VCO***
***vcr***
.subckt vcr cpout a1
mp1 a1 a1 vdd vdd pch_tn l=0.18u w=5u
mn1 a1 cpout gnd gnd nch_tn l=0.18u w=2u
mn2 a1 a1 a2 gnd nch_tn l=0.18u w=2u
mn3 a2 cpout gnd gnd nch_tn l=0.18u w=2u
.ends vcr
********
***********
Xvcr cpout a1 vcr
***********
****cell*****
.subckt vcocell outa outb ina inb 1
mp11 outa a1 vdd vdd pch_tn l=0.18u w=5u
mp12 outa outb vdd vdd pch_tn l=0.18u w=5u
mp21 outb outa vdd vdd pch_tn l=0.18u w=5u
mp22 outb a1 vdd vdd pch_tn l=0.18u w=5u
mn11 outa ina gnd gnd nch_tn l=0.18u w=1.9u
mn12 outa outb gnd gnd nch_tn l=0.18u w=1.9u
mn21 outb outa gnd gnd nch_tn l=0.18u w=1.9u
mn22 outb inb gnd gnd nch_tn l=0.18u w=1.9u
.ends vcocell
****************
***********
Xdc1 out1 out2 out5 out6 a1 vcocell
Xdc2 out3 out4 out1 out2 a1 vcocell
Xdc3 out5 out6 out3 out4 a1 vcocell
************
*************************DIV*******************
*********Divider***********
.subckt div ck out
mp1 d1 d2 vdd vdd pch_tn l=0.18u w=5u
mp2 d3 ck d1 vdd pch_tn l=0.18u w=5u
mn1 d3 d2 gnd gnd nch_tn l=0.18u w=2u
mp3 d5 ck vdd vdd pch_tn l=0.18u w=5u
mn2 d5 d3 d6 gnd nch_tn l=0.18u w=2u
mn3 d6 ck gnd gnd nch_tn l=0.18u w=2u
mp4 d2 d5 vdd vdd pch_tn l=0.18u w=5u
mn4 d2 ck d7 gnd nch_tn l=0.18u w=2u
mn5 d7 d5 gnd gnd nch_tn l=0.18u w=2u
mp5 out d2 vdd vdd pch_tn l=0.18u w=5u
mn6 out d2 gnd gnd nch_tn l=0.18u w=2u
.ends div
********************************
Xdiv1 out5 a div
Xdiv2 a b div
Xdiv3 b e div
Xdiv4 e f div
Xdiv5 f g div
Xdiv6 g fdiv div
*.param per='1n'
*.param tsi='19.9u'
.tran 1n 20u
.end

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[sharath666]

I can't make out anything from this code...Did you find the error in netlist simulations or RTL simulations?

 

[FvM]

Is it a handwritten SPICE netlist, what should we check it against? There should be a circuit schematic.

At first sight I notice a nonglobal floating gate node in the vcocell subcircuit, so I believe at least this circuit part won't work.