What's the typical value of a comparator input offset?

[guow06]

I'm designing a comparator for my 10-bit SAR ADC. Just wondering what's the typical value of the comparator's input offset with careful layout. For 10-bit ADC, do I need to do offset cancellation?
I have done a simple dynamic comparator and the post-layout simulation result shows about 1mV offset. Will it be better if I add a preamplify-stage? (The whole ADC post-layout simulation shows a good result without offset cancellation though)

 

[crutschow]

A preamplify-stage will also have an offset so that won't help.

One way to minimize offset is to use an autozero cycle which zeros the offsets in the comparator at the start of each A/D conversion. See this as an example.

 

[checkmate]

It's likely you did a post-layout without Monte Carlo.
This makes 1mV of systematic offset, which is very bad. I would assume that you have a low comparator gain.
Usually systematic offset is in the 100uV range, and random offset is in the mV range per sigma.

 

[vimalkhanna]

There is a deviation in types of input stage of comparators used for prestage ADC .These can be few microvolts to few millivolts.As such , you connot genralize this term.

 

[guow06]

View attachment untitled.bmp This is my dynamic comparator. I ran the Menta Carlo simulation with process and mismatch. The offset is around 1~2mV. So it is not so bad if my vlsb=1mV, is that right? Need for auto-zero?