What's the maximum tolerable offset, without digital error correction, in comparator?

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suhas_shiv

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Hi All,
I have a question regarding comparator offset in Pipeline ADC. What is the maximum offset u can tolerate with and without digital error correction?

Books I have read say +-Vref/4 with error correction. Suppose my input is 1V differential signal, does that mean max offset tolerable is +-0.125V( since Vref =0.5V and Vref/4=0.125V). Thanks for the help.
 

comparator Offset

Dear Suhas,

I think that it depends on the number of bits you resolve in each stage of the pipeline. Vref/4 would apply to about 2 bits per stage, if I am not wrong. Also, the residue gain is also critical in defining the required offset.
 

comparator Offset

I am using the 1.5bits per stage architecture and hence the gain in each stage would be 2.
 

comparator Offset

Then you would require the offset limitation to be about Vref/4 for your comparators
 

Re: comparator Offset

Vamsi Mocherla said:
Then you would require the offset limitation to be about Vref/4 for your comparators
Click to expand...
can you tell me why is Vref/4?
and what kind of references I should read???
 

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