suhas_shiv
Full Member level 2
Hi All,
I have a question regarding comparator offset in Pipeline ADC. What is the maximum offset u can tolerate with and without digital error correction?
Books I have read say +-Vref/4 with error correction. Suppose my input is 1V differential signal, does that mean max offset tolerable is +-0.125V( since Vref =0.5V and Vref/4=0.125V). Thanks for the help.
I have a question regarding comparator offset in Pipeline ADC. What is the maximum offset u can tolerate with and without digital error correction?
Books I have read say +-Vref/4 with error correction. Suppose my input is 1V differential signal, does that mean max offset tolerable is +-0.125V( since Vref =0.5V and Vref/4=0.125V). Thanks for the help.