module bin_bcd_counter(/*AUTOARG*/
// Outputs
counter,
// Inputs
clk, reset_n, cnt_bcd
);
input clk, reset_n;
input cnt_bcd;
output [7:0] counter;
reg [7:0] counter;
reg [7:0] counter_nx;
always@(posedge clk or negedge reset_n) begin
if (!reset_n) begin
counter <= 0;
end else begin
counter <= counter_nx;
end
end
always @(/*AS*/cnt_bcd or counter) begin
counter_nx = counter + 1;
if (cnt_bcd) begin
if (counter_nx[3:0] > 9) begin
counter_nx[3:0] = counter_nx[3:0] + 6;
counter_nx[7:4] = counter_nx[7:4] + 1;
end
if (counter_nx[7:4] > 9)
counter_nx[7:4] = counter_nx[7:4] + 6;
end
end
endmodule // bin_bcd_counter