What's the difference of LDD, DDD and LDMOS transistors

[woodman]

what is ldmos

When I read the book 'The Art of Analog Layout', I have the question:
What's the difference of LDD, DDD and LDMOS transistors?
the other question is that what's the relationship between these transistors and
DMOS?

Thanks a lot!

 

[Vamsi Mocherla]

double diffused drain

I hope that this answers your questions fairly...

1.LDD is Lightly Doped drain. If a MOSFET has a LDD structure, the built in potential, Vbi in a LDD-MOSFET will be smaller as compared to conventional MOSFET’s; therefore thethreshold voltage reduction due to the short channel effect will be smaller

2.I do not know what DDD is.

3.LDMOS is laterally diffused MOSFET. It is used in HF,RF applications. In the LDMOS the source is formed near the body on the p -sub isolated by epitaxial layer. The advantage for this configuration is that, there is no gain reduction and the performance is bettered.

 

[DoctorProf]

ddd ldmos

LDD = Lightly Doped Drain, Special implant placed in the drain near the gate to reduce the electric field at the drain. It is used to control hot carrier degradation by decreasing the impact ionization in the drain.

DDD = Double DIffused Drain, Drain construction using two dopings that difuse at different rates(P and As). The faster diffuser (P) will create a lower doped region near the gate/drain edge hence lowering the electric field. It is also used for hot carrier improvement

LDMOS = Lateral DMOS Transistor, This is a high voltage transistor design where the drain is designed to have a lower doped diffusion that allows it to handle higher voltages without damage to the gate.

 

[woodman]

ldmos layout

Thanks!
I get it!
But what is DMOS?

 

[DoctorProf]

ldmos p body

DMOS = Double diffused Metal Oxide Semiconductor

The LDMOS device construction is much different from the DDD device. In the DDD device you want to create a small region of lighter doping without impacting the transistor parameters. In the LDMOS you have a much larger "Drift" region to support the higher voltages the LDMOS drain is design to have. High voltage is also relative. In a 1.3 volt process high voltage may be 5 volts. I also know that it could be 40 volts or higher. High voltage is relative to the native voltage of the standard NMOS transistors in the process.

Dr.Prof