Whats the difference between clock buffering and CTS..?

[giggs11]

hi,

I'm quite quizzed about the difference between Clock Buffering, CTS and Clock Trees. This is what I vaguely understand:

Clock Buffering refers to insertion of stages of buffers to drive the heavy load of the clock signal. Confined to a relatively small module.

CTS involves symmetric routing of the clock signal to the various modules in a system design. The idea is to connect the clock signal symmetrically to all modules in the system to avoid clock skew due to wire capacitance. Buffering is also done at this stage to drive the load of the clock signal to all modules in design.

Clock trees refers to the tree-structure adopted in CTS to distribute the clock.

Please comment on these definitions. Is it also possible to design till tape-out without performing Clock Analysis. What is the main effect of such leaving out the clock analysis stage.

Thanks.

 

[eexuke]

clock design is always in parallel with back-end design. Without detailed and accurate clock information, you can not get proper results of timing information,such as setup/hold timing, thus can't gurrantee the proper function of your design.

 

[rol73]

CTS = clock trees synthesys
Clock tree = a structure for clock buffering

Each flop in your design must receive (and sense) clock input at the right instant, to ensure correct output (i.e. no timing violations): then you need to control your edges and your skew on clock lines...

Clock analysis is a must for each digital designer!!!