No -- the Student version can't the vendor cell-libraries. (You need these for gate-level simulations, or if your RTL directly instantiates any vendor IP-blocks, like the DSP48, BlockRAM, transceiver, etc.)
The XE edition (free-one) comes with Xilinx's libraries precompiled. I'd start there.
And like someone else said, none of the free Modelsim editions (OEM or Mentor) allow mixed-language (VHDL+Verilog) simulation. I also noticed Systemverilog support has been disabled since last year. (Before that, you could compile and run limited Systemverilog simulations, if you limited yourself to 'Design' constructs only.)