Hi friend,
DIBL stands for drain-induced barrier lowering.
Considering a NMOS, when Vds increases with fixed Vgs, the depth of depletion region across the drain (n+) and the bulk (p+ fixed at Vss) increases [more reverse-biased]. As a result, less region across a MOS is needed to be depleted, and then form a channel.
Vt threshold voltage is the minimum voltage needed to be applied to the gate in order to form a channel in the MOS. To form a channel, the region across a MOS is needed to be first depleted by increasing the gate voltage, then a channel is formed if we continue to do so.
In conclusion, if we increase Vds, less region across a MOS is needed to be depleted and thus less gate voltage is required to form a channel across a MOS.
Please advise me if I have made any mistake ~
Will