module rt_image( //this is your top level... where you would constrain the phisical pins to the these ports.
input wire clk, <-- your clk net
input wire ser_rx,
output wire ser_tx,
etc.....
);
// UART
wire [7:0] out_port;
reg en_16_x_baud;
wire write_to_uart;
wire tx_full;
wire tx_half_full;
reg read_from_uart;
wire [7:0] rx_data;
wire rx_data_present;
wire rx_full;
wire rx_half_full;
wire [7:0] uart_status_port;
assign uart_status_port = {3'b000,rx_data_present,rx_full,rx_half_full,tx_full,tx_half_full};
uart_tx transmit (
.data_in(out_port),
.write_buffer(write_to_uart),
.reset_buffer(1'b0),
.en_16_x_baud(en_16_x_baud),
.serial_out(ser_tx),
.buffer_full(tx_full),
.buffer_half_full(tx_half_full),
.clk(clk)); //.clk(clk100)); <-- note modded code here to connect you clk net to the Uart clk
uart_rx receive (
.serial_in(ser_rx),
.data_out(rx_data),
.read_buffer(read_from_uart),
.reset_buffer(1'b0),
.en_16_x_baud(en_16_x_baud),
.buffer_data_present(rx_data_present),
.buffer_full(rx_full),
.buffer_half_full(rx_half_full),
.clk(clk)); //.clk(clk100)); <-- note modded code here to connect you clk net to the Uart clk