high speed ADC
to yagi
for case 2
Doudle sampling tech usually applied in filters,ΔΣ modulators and pipelined ADCs without speed up the OTA. But OTA'srecovering time may affect doubling the sampling speed. While double sampling need more switches, which can produce more distortion in T/H.
following papers may help u
[1] T. C. Choi, R. W. Brodersen, Considerations for High-Frequency
Switched-Capacitor Ladder Filters, IEEE Trans. Circuits and Systems, vol.
cas-27, pp. 545552, Jun 1980.
[2] D. Senderowicz, G. Nicollini, S. Pernici, A. Nagari, P. Confalonieri, C.
Dallavalle, Low-Voltage Double-Sampled Converters, IEEE J. Solid-
State Circuits, vol. 32, pp. 19071909, Dec. 1997.
[3] S. Bazarjani, M. Snelgrove, A 40 MHz Double-Sampled SC Bandpass
Modulator, in Proc. IEEE International Symposium on Circuits and Sys-
tems, 1997, pp. 7376.
[4] W. Bright, 8b 75MSample/s 70mWParallel Pipelined ADC Incorporating
Double Sampling, in 1998 IEEE International Solid-State Circuits Confer-
ence, Dig. Tech. Pap., pp. 146147, 1998.
and for ur case 1, the overlap period of clock is much less than 0.8ns, and 4.2ns is enough for OTA to settle when 1V-Vpp and 100Mhz speed.
Added after 15 minutes:
To yaqi
I noticed that you read the paper
"10b 200Msps CMOS parallel pipeline ADC"
and got confused by double sampling.
while i think T/H 's OTA does not operate in 100Mhz. The paper represents a paralled pipelined ADC, so it has at least 2 slice of pipelined ADC, which means each slice operate at 100Mhz. As a result, Double sampling T/H has doubled loads. That challenge the design a lot.
regards