what's meaning about those in PT

[mic_huhu]

Dear all,

I used report_clock_timing to look for the longest and shortest clock path .

1) At first , I used -type summary .I found the report said "maximum launch latency" and "minimum capture latency"

2) I used -type latency -nworst 1 .the report said th" maximum lauch latecy" point is the same as above. the defult used "-launch"

3) When I used -type latency -nworst 1 -capture .the point is same with "minimum capture latency" point in the first summary report.

So I am confused .what are the lauch latency and capture latency.? and why the third report is different with the second report ? what are on earth the longest clock latency path and the shortest clock path?

hope you can clear me

thanks advance.

Johnny

 

[spauls]

Dear,
Check the latency value of source clocks in your constraints,
and cross check with physical design guys.

 

[claint]

Hi, the clock pin of every register has different path delay from the source clock pin.
launch latency is the clock path delay the lauched register which lauch data on the Q/Qbar pin.while the capture lantency is the clock path delay the captured register which capture data on the D pin. To check setup, the lauch latency use the maximum while capture latency use the minmum. It is the opposite in hold situation.

Added after 2 minutes:

I am sorry ,
launch latency is the clock path delay of the lauched register which lauch data on the Q/Qbar pin.while the capture lantency is the clock path delay of the captured register which capture data on the D pin.