1) we should know that depletion width is directly proportional to the squart root of the applied reverse bias [e.g. W = k * sqrt(Vr)]. It means we should expect the depletion width will be a kind of constant even we further increase the reverse bias.
2) based on the knowledge we have in 1), if the silicon for current conduction is too wide, no matter how large the reverse bias you applied to the JFET, there is still a un-depleted silicon, which makes a finite leakage current that you cannot control by the "gate".
However, if the JFET is a commerical device, this should not be happened......
Anyway, hope this help
Scottie