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What's happening in JFET during the pinch-off region?

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mystique_unbound

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In JFET operation during the pinch-off region what is hapenning ? When the width is reduced the current should decrease . But the current is constant at pinch off region . Why is it so ? Need clear explanation fron physics point of view ?
 

paulux

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Re: about JFET

The electrons drift across the pinch-off region that you can think of a high value "resistor" but this "resistor" does not show linear relationship between the potential across this "resistor".
 

scottieman

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Re: about JFET

mystique_unbound said:
In JFET operation during the pinch-off region what is hapenning ? When the width is reduced the current should decrease . But the current is constant at pinch off region . Why is it so ? Need clear explanation fron physics point of view ?

1) we should know that depletion width is directly proportional to the squart root of the applied reverse bias [e.g. W = k * sqrt(Vr)]. It means we should expect the depletion width will be a kind of constant even we further increase the reverse bias.

2) based on the knowledge we have in 1), if the silicon for current conduction is too wide, no matter how large the reverse bias you applied to the JFET, there is still a un-depleted silicon, which makes a finite leakage current that you cannot control by the "gate".

However, if the JFET is a commerical device, this should not be happened......

Anyway, hope this help
Scottie
 

huojinsi

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Re: about JFET

mystique_unbound wrote:
In JFET operation during the pinch-off region what is hapenning ?
During the pinch-off, the conducting channel of JFET is pinched off by depletion region,and the conducting channel disappears.
When the width is reduced the current should decrease . But the current is constant at pinch off region . Why is it so ?
During the pinch-off, the resistance of conducting channel is very large, and it is approximately equivalent to infinite. Because the resistance between drain and source is infinite during the pinch-off, the current between drain and source has no relation with the Vds and is constant.
 

rituparna dhar

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1) we should know that depletion width is directly proportional to the squart root of the applied reverse bias [e.g. W = k * sqrt(Vr)]. It means we should expect the depletion width will be a kind of constant even we further increase the reverse bias.

2) based on the knowledge we have in 1), if the silicon for current conduction is too wide, no matter how large the reverse bias you applied to the JFET, there is still a un-depleted silicon, which makes a finite leakage current that you cannot control by the "gate".

However, if the JFET is a commerical device, this should not be happened......

Anyway, hope this help
Scottie

3.during pinch off region gate to souce voltage is 0..nd as drain 2 source voltage has no relation with the drain current..it becomes constant..
 

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