I have checked the datasheet, but I didn't really much understood it, and tried to compare it to the picture of what author got.Review 74165 datasheet. It has timing conditions (e.g. setup delay between SH/LD and CLK) that must be met for correct operation. If setup requirements are violated, logic output isn't predictable.
Hello !Back in 1976 I designed a UART with small scale logic using the setup and hold times to make it work. You just need to follow the timing for prop delay, setup and hold times to make it work when signals are synchronous.
I would expect that CLK edge is ignored if it's coinciding with SH rising edge (SH = 1 setup time of zero). But this side of nLD/SH to CLK relation isn't exactly specified. In any case there's a range where DFF output isn't predictable.
In any case there's a range where DFF output isn't predictable.
Please notice that nLD/SH is driving asynchronous DFF inputs. Don't confuse the problem with synchronous D to CLK setup/hold time.
SH/LD is async and overrides edge-triggered Clk always!Hello !
That's why I've asked why it worked in that case. How should I interpret that SH/LD and CLK have the same rising moment because they are both synchronized. I read something in the datasheet that I didn't much understand and tried to come up with the explanation, why it worked in that case (good to notify the CLK_INH in this case is always 0, author grounded this pin). So this SH/LD and CLK rising at the same time is confusing and I can't explain why it worked thus can't imagine what it interprets it as "0" or "1". It's hard to explain.
I see from the post that it's about delays but I don't see them in the video because the same rise is passed to both inputs at the same time, so the delays are the same I guess ? So D flip flop doesn't know if it's "0" or "1" so it's a hazard ? But it happened to be always "0" in this type of situation which I don't understand looking at video osciloscope and knowing that both CLK and SH/LD get the same bit from the same output which is shown in the osciloscope (or maybe they get from different output but on the osciloscope it matches).
I don't get it ...
View attachment 186417
Looking at this also confuses me because like I said both of them raises, and maybe they are delayed but I don't see it exactly (on the osciloscope of the video) and how it was achieved and how he was sure (it wasn't explained how it worked for him the author just plugged it).
And it a bits breaks my logical thinking here because I always interpreted these type of situations as logic hazard ? Or something that give unpredictible output.
View attachment 186418
Usually in tutorials about D flip flop they don't show the situations when CLK and D are both rising at the same time, and here the SH/LD and CLK are the same type of situation.
PS.
Yes the purple/pink is imposes a yellow signal in the osciloscope (yellow is the CLK, purple is passed to SH/LD) so the yellow is not visible under purple/pink because they are I think identical ? If so where there is delay that makes both rising signals workand makes even if SH/LD is rising the D flipflop will read SH/LD as 0 and not as 0/1 because its rising.
I don't get it ...
SH/LD is async and overrides edge-triggered Clk always!
This basically answers why CLK input is ignored. The additional question is about SH/LD setup and hold time. The video refers to 74LS165, I have TI datasheet at hand.SH/LD is async and overrides edge-triggered Clk always!
SH/LD is async and overrides edge-triggered Clk always!
This basically answers why CLK input is ignored.
The additional question is about SH/LD setup and hold time. The video refers to 74LS165, I have TI datasheet at hand.
If we read it so that "any input" th also applies to SH/LD, applying CLK edge and SH =1 simultaneously isn't guaranteed to prevent CLK action. We have a range of 0 to 10 ns delay between SH=1 and CLK edge with undefined result.
Not sure about the exact SH/LD timing in the video, didn't attempt to decode the circuit. Either there's an additional small delay or it's operating only by chance.
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