What will be the output of this verilog code Any Idea ?

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shethpurak

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reg Var1;
initial begin
Var1<= "-"
end
In
 

I'm not sure. A reg can only be a 1, 0, X or Z, so I'm not sure what assigning it to a "-" will do. May depend on the simulator.
 

I believe that Var1 will be assigned bit 0 of the 8 bit ASCII value of the character -. The simulator or the synth. tool should give a warning about truncating.
 

it is mostly simulator dependent.

I ran got it to be 1
 

it is mostly simulator dependent.
Click to expand...

It should not be simulator dependent.
It will take ASCII value and assign LSB bit to Var1.
 

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