Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

What will be the output of this verilog code Any Idea ?

Status
Not open for further replies.
S

shethpurak

Junior Member level 1
Joined
Nov 15, 2005
Messages
15
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,399
reg Var1;
initial begin
Var1<= "-"
end
In
 

I'm not sure. A reg can only be a 1, 0, X or Z, so I'm not sure what assigning it to a "-" will do. May depend on the simulator.
 

I believe that Var1 will be assigned bit 0 of the 8 bit ASCII value of the character -. The simulator or the synth. tool should give a warning about truncating.
 

it is mostly simulator dependent.

I ran got it to be 1
 

it is mostly simulator dependent.
Click to expand...

It should not be simulator dependent.
It will take ASCII value and assign LSB bit to Var1.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top