A good rule of thumb is for the estimated wirecap per fanout to be the same as the input gate cap of the largest inverter using a single P and N transistor. If you've got lots of gates, or are simply cautious, you can increase this value by say 50%.
-Graham
I agree, below .18 real environment should be considered for delay calculation. If you still use DC, your convergence cycle will be enlarged, and many many useless buffer, inverter will be introduced.