Synthesis will not infer an adder if synthesis tool is not aware of any library that has adders. In the absence of an adder library, Synthesis will just create gate netlist ( consisting of AND, OR, XOR gates etc) that will achieve the functionality of an adder
Synthesis will not infer an adder if synthesis tool is not aware of any library that has adders. In the absence of an adder library, Synthesis will just create gate netlist ( consisting of AND, OR, XOR gates etc) that will achieve the functionality of an adder
Synthesis will infer an adder whenever it sees a '+' sign in your code, and implementation varies for sure.
Either way, OP is asking about adder architecture, not the components that can be used to make an adder.
use this in genus/rtl compiler/dc. turn all the debug messages on, highest level. you can literally see the tool saying ADDER INFERRED in the log. implementation varies, as explained.
please do the later part of synthesis using Design Compiler or RTL compiler (without any library support) and paste the result here. I don't have access to these tools any more.