What tools are needed for full ASIC flow?

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p_shinde

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hi.

if i am rgt SOC Encounter is for RTl-- GDSII, so does it covers full ASIC flow???

no other tool required if we go for SOC???

indsutry ppl reply soon.

thanks in advance

Prasad
 

Re: Encounter

To make into a full ASIC flow you need to use sign-off tools like PrimeTime for post

layout STA sign-off, Caliber for DRC,LVS sign-off and some power analysis tools like

voltage storm etc. You can use Encounter only for Implementation
 

Encounter

SOC ENCOUNTER can covers full ASIC flow.
 

Re: Encounter

Yes Encounter covers the full flow, as said you may need caliber for sign-off DRC. Also you may need additional licences of CeltIC for signal integrity.
 

Re: Encounter

so .. it still need third-party or assura for its physical verification.

BRs
 

Re: Encounter

You need PT for timing sign-off
 

Re: Encounter

so which type of companies or for which type of ICs uses Encounter??

as i guess every company has different tools for an ASIC flow, so want to know where is Encounter is used ?


Prasad
 

Re: Encounter

Encounter is used in the Industry for Physical implementation of chips. Lately lot of

companies or using the tool. Its a good tool
 

Re: Encounter

SOC Encounter has covered whole RTL-to-GDSII implementation flow.
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Majorly ...

1) First Encounter(FE) has been widely used in Prototype/Floorplan/Power Plan tasks even before it has been acquired by Cadence.

2) RTL Compiler(RC) has been adopted to do RTL-to-gate level logic synthesis recently. (It used to be Get2Chip's product before merged by Cadence.)
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