There is a function for 'Add delay paths' in TetraMAX that require a file for delay path, and I think I have to use .sdf file for it.
Am I correct?
or maybe there is another file that I should use?
Can someone tell me which tool should I use to generate .sdf file to be used for path delay fault detection in TetraMAX?
Is it PrimeTime @ Design Compiler @ any other software?
Hi,
During synthesis rtl is converted into logic gates , flops etc ..... generally in synthesis
the timing parameters are not set properly. So, after the netlist generation we go for bcs & wcs timing simulation to verify whether the timing parameters are met during synthesis or not.
The .sdf file contains all the timing related informations of all the gates ie delay between I/P and O/P of a particular gate.