What to consider when designing a asynchronous FIFO?

[pintuinvlsi]

Hi,
Can anybody tell me what are the factors i have to consider while designing a async FIFO?
Again While desinging fifo why we code write and read pointer in gray code not as a simple counter??

Thanks,
pintuinvlsi

 

[alam.tauqueer]

Asyc Fifo design

IN Async FIFO u need to focus more on metastalbility.We use gray code because in case of gray code only one bit will change when pointer increase which help to synchronise the two clock domain (write and read clock).
For more information search one google u ll get good material on it.

 

[ALUOp]

Re: Asyc Fifo design

Oh man, you really need to read this classic paper.
Highly recommended.

http://www.sunburst-design.com/papers/CummingsSNUG2001SJ_AsyncClk.pdf

 

[kanthu555]

Re: Asyc Fifo design

please send me fifo to calculate depth of fifo to me.

Oh man, you really need to read this classic paper.
Highly recommended.

http://www.sunburst-design.com/papers/CummingsSNUG2001SJ_AsyncClk.pdf

 

[bharat_in]

Re: Asyc Fifo design

Can anyone provide an equation to calulate the depth of async fifo?

 

[beta0]

Re: Asyc Fifo design

Can anyone provide an equation to calulate the depth of async fifo?

 

[phoenixfeng]

Asyc Fifo design

SNUG has two papers about the async fifo which are sytle1 and sytle2
but when u read sytle2, be careful about the asyschronous reset&set signal for empty&full, i think there are some problems, which are glitches.