what to check before starting the Physical design flow

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jitendravlsi

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Please tell me what to check before starting the floorplan in soc encounter and how to check them?
 

Import the gate level verilog netlist , SDC and check the timing by running "check_timing" command.

Which will give you the rough timing, missing timing constraints if any in the SDC etc...
 

    jitendravlsi

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by using the "checkDesign" command in soc encounter we can check check for the following data:

 Physical library
 Timing library
 Netlist
 I/Os
 Tie-high and tie-low pins
 Power and ground pins

but i dont know how to check timing parameters or we can say sdc..

Dear arjun are you sure about this command in soc encounter?
 

Hi Jitendra,

I have uploaded timing closure in soc encounter document. Go through "Data preparation section I guess which will answer your questions".

Let me know if you still have any doubts.

Regards
 

    jitendravlsi

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thanks arjun.....

really helpful doc
 

    V

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