What to check after logic synthesis?

[ivlsi]

Hi All,

What should I check after logic synthesis?

As for me, here is the list:
1) Timing Warnings (negative slacks)
2) Gate Count

What am I missing?

Thank you!

 

[jbeniston]

Power.
ATPG fault coverage.
Logical equivalence of RTL to netlist.
Missing timing constraints.