In general, I would care about long line resistance, RC delay, capacitive coupling (accepting or introducing noise from/to other nets).
For current paths - IR drop (because of high resistance).
For voltage paths - capacitive coupling, introducing noise.
For extraction and post-layout analysis - do not forget to tell the extraction tool to fracture the line (set the maximum allowable fracturing length), otherwise all coupling capacitance will be assigned to the end points (if there are no fractures / vias / bents in this line), and your AC / transient response will be wrong, in post-layout simulations.