lnuhcs
Newbie level 4
In a wishbone soc platform,the bus is 32 bits,but some state or control registers in some slave IP is 8bits.In this cases ,a signal SEL_O is always used to choose which byte is selected on the bus.My question is ,How Does CPU dual this selc_o signal and the register address.Does sel_o and address has some contact?
sel_o is described as:
The select output array [SEL_O()] indicates where valid data is expected on the [DAT_I()] signal
array during READ cycles, and where it is placed on the [DAT_O()] signal array during WRITE
cycles. The array boundaries are determined by the granularity of a port. For example, if 8-bit
granularity is used on a 64-bit port, then there would be an array of eight select signals with
boundaries of [SEL_O(7..0)]. Each individual select signal correlates to one of eight active bytes
on the 64-bit data port. For more information about [SEL_O()], please refer to the data organization
section in Chapter 3 of this specification. Also see the [DAT_I()], [DAT_O()] and [STB_O]
signal descriptions.
sel_o is described as:
The select output array [SEL_O()] indicates where valid data is expected on the [DAT_I()] signal
array during READ cycles, and where it is placed on the [DAT_O()] signal array during WRITE
cycles. The array boundaries are determined by the granularity of a port. For example, if 8-bit
granularity is used on a 64-bit port, then there would be an array of eight select signals with
boundaries of [SEL_O(7..0)]. Each individual select signal correlates to one of eight active bytes
on the 64-bit data port. For more information about [SEL_O()], please refer to the data organization
section in Chapter 3 of this specification. Also see the [DAT_I()], [DAT_O()] and [STB_O]
signal descriptions.
