what steps to take if a project isnt working?

[romikot]

What do i need to do if my project in the simulation is working flawlessly but when i try it on the board itself is giving me weired problems.
initialy i thoght maybe there is a problem with timing but i checked and everything seems fine.
(i have nexys 3 board).

 

[mrflibble]

I generally follow this easy step by step plan:

1 - jump up and down
2 - flail arms about
3 - sit down
4 - have some coffee
5 - debug

Should "debug" not be specific enough, I suggest giving more details.

 

[jeffrey samuel]

the prime fact in any mis circuiting is simple human error which we overlook many times better give your heart and soul to go through the connections again before posting your reply

most simulators use ideal standards and so the atmospheric effect on the designed ckt is 0 so there is a probability of some errors due to atmospheric effect also but in reality i have never faced it

 

[zalmonox]

OK here is what you can do. It happened to me and I guess I pinpointed the two main culprits here:
1) you can try to spot all the "undefined" signals in your code in order to make these signals proper '0' or '1'.
2) do you have some asynchronous resets created from synchronous logic. If yes try to eliminate all async. resets that are not the main power-up reset ...

Also:
3) avoid all 'H' and 'L' in your code
4) try to see if there are functional errors
5) pinout constraints not correct / time constraints not correct or complete

And if all this fails )) try to find the hypothesis you make and is not true in reality <=== This is always a winning exercise.

Goodluck,

 

[romikot]

OK here is what you can do. It happened to me and I guess I pinpointed the two main culprits here:
1) you can try to spot all the "undefined" signals in your code in order to make these signals proper '0' or '1'.
2) do you have some asynchronous resets created from synchronous logic. If yes try to eliminate all async. resets that are not the main power-up reset ...

Also:
3) avoid all 'H' and 'L' in your code
4) try to see if there are functional errors
5) pinout constraints not correct / time constraints not correct or complete

And if all this fails )) try to find the hypothesis you make and is not true in reality <=== This is always a winning exercise.

Goodluck,

Hi
Thanks for your detailed response. Im new to fpga and will be glad if you can clearify on a few things.
1)whats an "undified signal??
2)I dont have asynchronous rests. But i would like to know how can it make the hardware not work?(my code is syntisised).
3)whats 'H' and 'L' ??
4)how can i see if there are functional errors? (the simulation is working-testbench and all).
5)pins and time constraints i checked and everything is ok!
I did a binary division between two numbers.
I dont know how can i change the code,couse the simulation is working and its has no warnings when its get syntisised.

 

[TrickyDicky]

Without seeing any code, any suggestions are just guesses. My guess is you wrote bad code.

 

[yourcheers]

Can you be more specific about what you are doing? and what is not working?

 

[jeffrey samuel]

all point to one thing that is manual calculation error so kindly post either a schematic or code for us to work on

 

[lucbra]

Also, the quality of the simulation, stands or falls with the quality of the testbench...

Assuming you covered all the corner cases of your design in the testbench, you have good chance that the design will work after a short debug session. Chipscope or simular might help with this process. But usually the corner cases aren't covered and/or wrong assumptions were made.
Code review by someone else helps, a testbench written by someone else is helping a great deal.