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what role does boundary scan and jtag play in dft

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phutanesv

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dear Dude,

Boundary scan circuitry can result in a complex environment for the internal scan structure and the ATPG process.
The two main issues with
boundary scan circuitry are 1) connecting the boundary scan circuitry with the internal scancircuitry, and
2) ensuring that the boundary scan circuitry is set up properly during ATPG.

To connect this boundary scan circuitry we make use of JTAG

Still many things to explain, but its lenghty

Phutane
 

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gold_2007

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phutanesv said:
dear Dude,

Boundary scan circuitry can result in a complex environment for the internal scan structure and the ATPG process.
The two main issues with
boundary scan circuitry are 1) connecting the boundary scan circuitry with the internal scancircuitry, and
2) ensuring that the boundary scan circuitry is set up properly during ATPG.

To connect this boundary scan circuitry we make use of JTAG

Still many things to explain, but its lenghty

Phutane
can u send me files that could help me regarding this ?
 

phutanesv

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Dear Dude,

I have hand written notes regarding this , and it too covers lot of pages.

I will try information , such that i can post in the Forum

Phutane
 

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ameed

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hi all,

following text can help you :idea:
In many more instances these days, boundary scan’s embedded infrastructure has been adopted by related test technologies. For example, microprocessor emulation testing historically has been a technique for microprocessor code debug and functional design validation. But because it takes advantage of the chip- and board-level access provided by boundary scan, processor emulation testing can be thought of as complementary to JTAG.

With systems such as ASSET’s Extended JTAG Coverage, boundary scan can validate the structural integrity of systems and PCBs, and emulation tests the functionality of various devices and subsystems. Combining these two methods gives engineers structural and functional test coverage on the same test platform, and this can simplify the overall test process, increasing productivity.

To capitalize on the strengths of both JTAG and emulation testing, several design practices should be followed. First, carefully plan the boundary scan TAP interface on a circuit board so that access to the CPU and the entire scan path is provided. Some emulation tools do not tolerate other JTAG devices on the scan path during emulation testing. If so, a method for targeting only the CPU during emulation testing will be needed.

In addition, most emulation tools do not support scan-path gateway or management devices. As a result, these tools cannot manage the scan path during emulation tests. Multiplexers that can be controlled by non-boundary scan signals can be implemented instead of JTAG gateway devices. Ultimately, it is better to perform structural JTAG tests first and then apply emulation-based functional tests after the structural integrity of the board has been verified.

Another new technology that rides on top of embedded boundary scan is the IEEE 1149.6 Boundary Scan Standard for Advanced Digital Networks. Unlike the original boundary scan IEEE 1149.1 standard that defines a static DC test technology, 1149.6 specifies a test methodology for chip-level interconnects that are dynamically AC coupled or feature differential signaling.

Prior to 1149.6, the static DC nature of 1149.1 prevented it from testing many of today’s increasingly popular high-speed buses. High-speed fiber-optic switching equipment, for example, already features hundreds, if not thousands, of these high-speed serial links.

Following a few guidelines during design will help implement 1149.6 tests later. Begin by reading and understanding the description in 1149.6 of possible implementations of AC coupling on high-speed IO signals. Since special 1149.6 cells must be designed into semiconductor devices to support 1149.6 testing techniques, as many 1149.6-compatible devices as possible should be specified for a given design. More and more 1149.6-compliant devices are being introduced all the time, but encouraging semiconductor vendors will certainly accelerate the pace.

Because of the newness of 1149.6, there sometimes will be instances when a 1149.6-compliant device will be interconnected through a high-speed AC-coupled signal to a device that is not 1149.6 compliant. When this happens, all of the 1149.6 fault coverage will not be achievable, but 1149.1 boundary scan tests still can be applied. A fully functional 1149.1/1149.6 boundary scan test system such as ScanWorks for High-Speed Buses will be able to take this into account.

The boundary scan tool should be able to support the following combinations:

• IEEE 1149.6 to IEEE 1149.6
• IEEE 1149.6 to IEEE 1149.1
• IEEE 1149.1 to IEEE 1149.6
• AC coupled IEEE 1149.1 to IEEE 1149.1

thanx......
 

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arpansen

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the basic idea of boundary scan is to figure out whether the chip interconnects work. an astounding majority of ICs today fail because the interconnects are damaged due to thermal or electrostatic or mechanical stress. with packaging becoming more complex a bed of nails testing is ruled out for more ICs. what would you do then? the idea of boundary scan is to simply capture the values from system pins of successive chips and then compare if they match or not. dft tools add on extra chip circuitry for such purposes on top of user design to achieve this functionality. you should start off by looking to IEEE 1149.1 standard.
 

shiv_emf

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Boundary scan and Jtag are same !!! pls correct me..

Aim for this testing is to check connections of chip on board are intact.
 

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