Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
hi,
what I mean is the transition time on input is depend on your system but not depend on design rule .
And I think if u have a good lib , for example Artisan library, you will find some transition design rule already exists in ur lib. So u dont have to redefine it.
And if u worry about the result of ur synthesis is not consistent with the result of p&r on max_transtion, u can try physical compiler.
For a non-linear delay model library, the output transition is a function of input transition and your output load. therefore if you define your input transition time and the output load your design is driving, then, there is no need to change_maximum transition which is already defibed in your vendor library(tsmc or ....).
hi, zyphor
your r correct. the max transition internal is depend on ur tech. but it's already set in ur lib by the vendor. so u can leave it alone. just care for the input transition. that's OK.
If it's a static signal path . It can be ignored .
Once it exsist in some critcal path . It may create the unwanted transition noise . When CMOS logic operate in its transistion , it looks not like a logic circuit anymore . It will act like a analog amplifier depends on the slop of transfer function . So once your power or input signal get small switching(for ex. 100mV) , it will amplify this noise to some scale(for ex. 100mV * 10 = 1V) . Thus make your logic malfunction . So it's better to constraint your max_transistion to a upper bound . The rule is the more short time in this unstable region(transition or amplifier mode) , the more reliable for your logic circuit .
max_transition defines the maximum time of logic-0-to-logic-1 as well as logic-1-to-logic-0. although the shorter the more reliable, shorter transition time also means a larger area. so the designer must know his/her system and trade-off.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
