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what makes the output frequency of DPLL stable?

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yellow_tulip_84

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Hi all,

When the Digiatl PLL works, it will generate high output freq based on the locking input freq. I'm currently studying about it. My big concern is WHAT characteristics make the output freq stable. And HOW the PLL will handle that work?

Anyone knows about it, plz explain. Thx in advance!
 

EngrAdnan

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output frequency of DPLL will be stable when the error voltage applied to VCO is near zero and its rate of change is low (within acceptable range), the proper filtering of error signal can reduce the frequency change of DPLL but remember introduction of a filter causes attenuation and delay(equals the number of samples = filter length), and these can effect other loop characteristics.
try reading PLL book by Dr R.E Best.
 

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