matrixofdynamism
Advanced Member level 2
Using open collector output means that when the output is driven low, some current will enter the IC as the transistor at the output is going to grounded. Remaining current shall enter the device on the other end. Now how much current shall enter the input device on the other end and how mucn into the driving open collector output buffer depends on the impedance of the two terminals. I assume that usually the input buffers of ICs have much lower input impedance than the output buffers but I am not sure how this can be confirmed.
Since some tiny current shall enter the driving buffer, there shall be some power dissipation in this driving IC. How does one know e.g for a 100s of pin FPGA or CPLD about how many outputs that are configured as open collector outputs, can be grounded at the same time? All devices have a limit on how much power they can dissipate before they burn out.
Since some tiny current shall enter the driving buffer, there shall be some power dissipation in this driving IC. How does one know e.g for a 100s of pin FPGA or CPLD about how many outputs that are configured as open collector outputs, can be grounded at the same time? All devices have a limit on how much power they can dissipate before they burn out.