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What kind of this netlist

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Junior Member level 3
Jun 18, 2002
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The netlist is in verilog. It seems it have been synthesised and all sentence is "assign" syntax but not gate level. So it can be synthesised again base on different technology lib. It's not RTL style verilog but more like a netlist.

Anyone knows what's this format? And how to achieve this?

According to your description, it seems to be the "structural" Verilog.
**broken link removed**

Verilog can be written in different abstract level:
1) Behavioral
2) RTL (Register Transfer Level)
3) Structural

not a_inv (a_not, a); // assign a_not = ~a;
not b_inv (b_not, b); // assign b_not = ~b;
and a1 (x, a_not, b); // assign x = a_not & b;
and a2 (y, b_not, a); // assign y = b_not & a;
or out (c, x, y); // assign c = x | y;
.... Anyone knows what's this format? And how to achieve this?
==> This kind of Verilog code may translated from the gate-level netlist of schematic-entry database.

From your description, it seems it should be verilog testbench generated from some tool like FastScan.

It could be the generic netlist exported from synthesizer(ex BG). Because it don't mapped to any std library cell, it can be re-feed to another synthesizer to generate the gate netlist at the target library. One usage I had heard is that RTL -> DC(BG) -> generic netlist -> synpifly -> FPGA's gate netlist -> FPGA' APR(ex, QuotaII for Altera device).


Thanks all.
I think maybe jarodz gave the right answer to me. I sometimes got verilog file for some modules in this style and I cannot see how it implement in detail. It's somehow boring me if I wanna change some behavior inside it. But maybe it's also the author's trap. He don't wanna someone else get to know more detailly how it implements.

Does anyway exist for translation this back to RTL?

In my opinion, It may be the result from the synthesis qithout the technology,ONLY provide the GTECH.

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