What kind of reset do FPGA D F/F have?

[telangamey_ei]

Hi,

This is a very general question but I am not able to find a proper answer to it.
May be I am not able to search it properly but it confuses me a lot.

My point is simple, What kind of a Flop do FPGA have in its SLICES?
I know its D F/F but the point is what kind of a reset do they have
its Async or Sync in any FPGA?

Thanks

 

[FvM]

The answer can be surely found in the datasheet or hardware manual of your FPGA family.

I admit that the various configuration options may be confusing at first sight.

In a short, all recent FPGA core DFFs have an asynchronous reset function. Some also an asynchronous set respectively asynchronous load input. But there's a tendency to omit the latter in newer FPGA series in favour of increased logic density.

By default, the asynchronous reset input is ORed with the device power-on reset.

Synchronous reset usually has to be (and always can be) implemented by logic programming means.

 

[telangamey_ei]

The answer can be surely found in the datasheet or hardware manual of your FPGA family.

I admit that the various configuration options may be confusing at first sight.

In a short, all recent FPGA core DFFs have an asynchronous reset function. Some also an asynchronous set respectively asynchronous load input. But there's a tendency to omit the latter in newer FPGA series in favour of increased logic density.

By default, the asynchronous reset input is ORed with the device power-on reset.

Synchronous reset usually has to be (and always can be) implemented by logic programming means.

---------------------------------------------------------------------------------------------------------------------------------------------------------------
Hi,

Thanks for your reply. Some how I am not able to find this description in any new FPGA data sheets.

But your post helps me to understand it clearly. My next doubt on this is when it comes to Sync. reset
how FPGA implements it. Does it tries to convert asyc. RESET FLOP to sync. using some logic (I knew whats
the logic is)? But, if it is it has to utilized LUT. But synthesis report never shows that it utilizes any LUT rather
it shows the utilization of REG only.

Thanks

 

[vGoodtimes]

you should check your FPGA documentation. For example, Xilinx devices tend to allow async or sync for either a set or reset. Virtex 5 had both set and reset. Altera device tend to have async load as a feature.

 

[FvM]

Some how I am not able to find this description in any new FPGA data sheets.

If you tell about the FPGA family we might help you to read it.

 

[telangamey_ei]

If you tell about the FPGA family we might help you to read it.

Hi,

Sorry for the delay, I am engaged in the project with hammer over my head and got relief today.

First again thanks for your support. I am referring to SPARTAN 6 UG384.
https://www.xilinx.com/support/documentation/user_guides/ug384.pdf

I went through couple of pages and I feel that it is having an asyn. reset. But I don't understand then how he implements
a syn. reset.

a) Does it utilizes a LUT for that (For logic implementation)?
b) If not then does each set of F/F has both type of circuit available with syn. and asyn. reset and depending upon the way we write a code it
simply selects which kind of a configuration it has to select and picks up the F/F accordingly?
c) If #b is true than do every FPGA has same type of implementation, I think no & if it is no then does those FPGA implements it using LUT?

Thanks

 

[FvM]

Everything is explained in the CLB user guide under Slice Description/Storage Elements. Reset can be configured as asynchronous or synchronous per Slice.