What kind of gate is used extensively in IC?

[Andy_Zhou]

Teacher told us that NOR gates can implement all circuits and it is the best gate for chips. Then when we describe a circuit using verilog, do we need keep in mind that we should avoid using of other gates?

Should we use following describe?

and A1(Out1,In1,In2);

And if we write that, what kind of circuit will be generated?

Thank you very much!

 

[Elc]

You can use any gate you want, but if you are going to implement you IC (sythesis) its better to use NOR and NAND gates. They are better for BJT and CMOS implementation.

 

[Andy_Zhou]

Sure we use verilog for implementing our IC, but if we confine our gates to NOR & NAND gates, I think our workload will be heavy. Do you think so? So I want to know the common solution for this issue.

by the way: now in chips what kind of implementation is widely used? Static CMOS? or dynamic CMOS?

 

[DrDolittle]

Iam working in supercomputing architecture.Here much of the harware implementation of algorithms are designed by NAND gate.The best example being Baugh-Wooley algorithm in which in the last step all the operations are transformed into NAND.

Regards
drdolittle

 

[qslazio]

NAND gate is more area saving than NOR gate.
So for High density applications, NAND is prefered

 

[arunragavan]

its always better using universal gates for implementation as it reduces the number of gates in implementing a logic.

In other words it takes fewer transistors to build a NAND gate than a AND gate.

Take a look at this.. this wud really help

h**p://www.cs.umass.edu/~weems/CmpSci535/Discussion6.html

with regards,

 

[andromeda]

One one of the rules in ASIC design is to use direct gate instantiation ONLY if it is absolutelly necesery (plese check for example Reuse methodology manual in EDA books). All high-level contructs are mapped into target ASIC library during synthesis.
ASIC library development ise separate from ASIC design (it is physical design). Libary is better if it includes more gate types. Libaries are different for normal and low-power technology. Todays libraries have all gates types and also AND-OR, OR-AND and other combination.

 

[tukken]

Yeah, I agree with andromeda,you should descript your design in easy reading and systhesis mode, if you focus your area, use right architecture and algorithm is important than use "any gate"

If you really reduce your area or increase you speed, you should in custom design.
Such as ALU or TLB