what is "USE hold register & MUX architecture"

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mallikmarasu

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hi to everyone,

what is "USE hold register & MUX architecture" ?

can any one explain clearly abt this one .

regards
mallikarjun
 

---------------
assign mux_out = sel ? flop_in : flop_out;

always @ (posedge clk2 or negedge rest) begin
if (!rst)
q <= 1'b0;
else
flop_out <= mux_out;
---------------

The use hold register & mux architecture is used as synchronizer at clock domain crossing. As shown in above code the signal flop_in from one clock domain is sent to flop flop_out in clock domain 2 only when the mux select line sel is high.

Normally the select line sel is passed through a double flop synchronizer and then used as select line for the mux.
 

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