timing constraints
TIG is "timing ignore". there are times when the tools find a timing constraint that is invalid.
for example, if there are two clocks that are related, say 100MHz and 200MHz, that were generated from the same PLL, then the tools might impose a 5ns constraint on all signals that pass between the clock domains.
But, async fifos might be used in the design. Such fifos will work between arbitrary clock domains. As such, the 5ns constraint isn't needed. TIG can also be used when the actual value of the logic isn't required to be 100% accurate at all times -- perhaps the logic is lighting a LED. TIG can sometimes be used on reset lines, though not always.