# What is this gold plating by the edge of the board??

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#### difflvl

plating on board edge

Can someone tell me what the gold plating around the edge of the board is, along with those tiny holes which look like very small vias. What is it for? And how can you make them in PCB programs?

I see this stuff often on cell phone boards.

Thanks

#### House_Cat

spacing of stitching vias

The gold is plated over copper for corrosion control. The area that you see around the board edge would be tied by vias to an internal ground plane. The small holes are stitching vias to tie the external ground area to the internal ground.

The purpose of the ground area and via stitching is to control EMI (electromagnetic interference) to and from the internal layers of the circuit board. It amounts to shielding that extends around the outside edge of the board.

You can make the same sort of areas with any PCB layout program by using fills, polygons, and traces. The stitching vias are placed at appropriate intervals by modeling the circuitry and determining the best separation for the vias based on the frequencies being shielded.

### difflvl

Points: 2

#### abhi002

##### Full Member level 5
House_cat,

As i remember,Placement of Stitching vias on the board required some calculations.for example,what sould between be distance between Stitching vias.

How to calculate that?

Regards,
abhi

#### House_Cat

I'm not aware of any equation or formulae that you can use to calculate the spacing of stitching vias.

The distance between vias would be a function of the frequencies involved, the dielectric, and the distance between the ground plane and the signal source. It would require some trial-and-error simulation in a 3D simulation program to find the optimum spacing.

Many designers avoid the simulation by simply placing stitching vias with random spacing, and taking a chance that it will work. If it doesn't, they respin the board. In my view, that is a sloppy way to work. Often, stitching vias are used in cases where none are necessary by folks too lazy to do the pre-routing analysis.

#### difflvl

Thanks housecat

Added after 3 hours 45 minutes:

I must say though, the vias look pretty random to me