What are the Ferrite Beads for powering Powering MGT

[engr_joni_ee]

I am reading a Xilinx document deals with Gigabit transceivers in which there is a section about PCB design guide to power MGTs. I have attached a picture which shows the placement of Ferrite Beads. What is that Ferrite Beads, is it a component to be place on the power traces ? or these are just via ?

 

[FvM]

The picture shows a differential pair with coplanar ground and via fence, nothing related to ferrite beads.

A document reference would allow us to check.

 

[engr_joni_ee]

You mean that this is like ground plane surrounded the differential pairs with ground vias at regular places.

I found that info in the book called "High Speed Serial I/O Made Easy". It is free book. I have attached the relevant pages.

 

[dick_freebird]

Many PI / SI experts rail against using beads. To me they are more of
a "patch" than a plan. But if you make the "bead" occupy the same
lands as (say) an available 0-ohm chip resistor / jumper then you
would have a free hand to play.

 

[engr_joni_ee]

But is that a component that called bead or the pattern how via are placed on the wide power trace ?

 

[FvM]

Ferrite beads are discussed on page 67 - 70 of the quoted publication https://www.xilinx.com/content/dam/xilinx/publications/archives/books/serialio.pdf

 

[engr_joni_ee]

Thanks for reply.
I am particularly interested in a table that provides part numbers for recommended ferrite beads suitable for high-speed design.
Unfortunately, the current version of the table in the document appears to be quite blurred and difficult to read, making it challenging to gather the necessary information.

Could you kindly assist in providing a clearer version of this table? Having access to this information in a more readable format would greatly help in my understanding
and decision-making process for the design.

I genuinely appreciate your support and assistance. Thank you in advance for your time and consideration.

 

[FvM]

It's just a snippet from the Murata data book and doesn't contain specific information for the FPGA power supply application. Confess that I didn't review the document details, just noticed that it has chapter discussing ferrite beads as power supply filters.

Most of the ferrite beads in the list are signal (low current) types, not suited for power supply nets. You can better refer to recent PCB design for FPGA board guidelines or development board BOMs.

 

[dick_freebird]

If I were you I'd call it a "cut and try, for later" and try to use an
assembly / package scheme which will let you stuff a series of
boards with a series of values so you can inspect the things you
truly care about, for real.

Regular old beads come in a variety of core materials and sizes.

I would imagine that a frequency-of-interest might be the serial
link 2/bitrate (for NRZ) where you need to supply the fundamental
(or have a big enough cap not to droop supply, against the load
ripple) but would like to start scraping off higher harmonics that
(at today's speeds) routed ESL will roll off their shunt effectiveness
(so the bead L, R are used to make the degreaded C, adequate).

But it's nuances all the way down so prepare thyself for combat.

 

[engr_joni_ee]

The PCB design guide for Xilinx UltraScale Architecture says "If powered by VCC_PSAUX, VCC_PSDDR_PLL must be filtered through a 120Ohm @ 100 MHz, size 0603 ferrite bead and a 10 μF or larger, size 0603 decoupling capacitor."

Question: Normally these power supplies (VCC_PSAUX, VCC_PSDDR_PLL) needs couple of Amps. Lets say they are designed for 5 A and the voltage is 1.5 V or 1.8 V. Can these small ferrite bead in package 0603 be used in series in power supply circuits delivering around 5 Amps ?

 

[FvM]

I would expect considerably lower supply current for these nodes. Ferrite bead current rating can be an issue nevertheless. The highest current rating I find for 120 Ohm 0603 is 3A (Murata BLM18KG121TN1, similar devices from Wuerth, Pulse, Samsung). Saturation and severe reduction of filter impedance can be expected already below rated current. In so far the suggestion sounds questionable.

 

[dick_freebird]

The PLL supply should be mA and the interest there is special.
Any ripple there will bleed forward into VCO phase noise that the
loop filter can't touch, fromt here into high speed serial link BER.

You can bet that to make their specs look good the vendor took
advantage of every supply- and ground-quality tweak to the test
hardware that they could, and didn't quite until they found the
best.

But now to get what they advertised and you believed, you must
do the same (or better; good luck).

Whether VAUX needs the same attention in fact, I do not know.
Might come down to what you use and what you use it for, from
the blocks powered from that rail.