What is the verification enviroment ?

[Anil Rana]

verification enviroment

Dear all
What is verification enviroment?Is it tool dependent or is a concept?If it is a concept how should one generate it,or what are methodologies for that?If there is any goo book or link on this matter plz post it.
Thanks to all .

 

[justin999]

verification enviroment

i think verification enviroment can not express exactlu by a word, it is tool dependent,　also it is verification method depend

 

[bravobravo]

Re: verification enviroment

Software verification env . ----> c mode and then its HDL code
+
Hardware verification env. --- > fpga .. and firmware...
+
Test chip ----> real chip .... and firmware...

 

[visualart]

verification enviroment

It include many matter.
according to the appilcation, is may be c mode, or a HDL testbench env, or the hardare patform, or an equipment.

 

[bismillah]

Re: verification enviroment

Hi,
Verification Environment is something which is created around DUT, it includes Test pattern Generators, Golden reference models, bfms etc.

 

[amaccormack]

Re: verification enviroment

Really, the Verification Environment is the whole set-up used to verify a design: the code, the scripts, the regression control, the tools used, the documentation and the methodology.

I'd expect someone joining a project's verification team to ask "So, how do you run the verification environment".

 

[bismillah]

Re: verification enviroment

Hi,
Verification Environment is something which is created around DUT, it includes Test pattern Generators, Golden reference models, bfms etc.

 

[soccer]

verification enviroment

i suggest you read the book of writing testbench. in this book you will learn essential concepts of verification includig your problem.

 

[brianhe]

Re: verification enviroment

To speak simply, verification is like to run simulation to verify that the function of your design is correct. So we normal call it functional verification to diff is from validation which normally use fpga to verification design.
Actually it is a complicated and time consuming process in the ASIC design flow.
If you spent about %30 on coding, then maybe you need %70 of your time to do verification.

A simple case is, you wrtie code for a full ADDER(the DUT, design under test) and you write a testbench and some test vectors to run simulation and test it.
That can be called verification, but it may not be complete. Since you must verif all the functions of the DUT and run code coverage to make sure that all the code have been covered/tested.

Only use verilog/VHDL to to verification is not enough and not efficient in most cases. So some high level language C/perl/python ... are often used. The testbench, or say the top level of your design is still hdl. We just use high level language to drive the DUT(stimulus), monitor it's output and compare the output data with the expected results.

There comes a lot of verification EDA tools and verification language. Such as vera, specman e. System Verilog is developed not only for verifcation, but right now it is mainly used for verifcation.

There are too many thing to talk about. Maybe you can search following key words from the internet

functional verification, testbench, specman, vera, BFM,

 

[Thomson]

Re: verification enviroment

simply put, it generates the stimulus and check the results.
As for the first portion, it shall comprise Constraints Control---->Generator/Packets---->BFM/Transactor to DUT.

As for the latter, the results shall be compared with the expected ones including the sequence or the data etc.

Currently some HVL is put up to ease or solve these problems.

You can refer to SystemVErilog.

 

[kinjal_book]

Re: verification enviroment

Making an environment which makes the verification easy.

It will contain generator [ to generate the data either direct or random]
BFM [Bus functional Model] -> this will drive the data to DUT
Monitor -> this will collect all data, check for the protocol and also functional coverage
Scoreboard -> Passing condition of the test,

Agent -> Which will generally contain, BFM, Monitor, coverage, checker

Env -> Collection of the agent + signal maps

The locations of the component may vary as per the requirement and DUT type.