What is typecal setting of transition time in CTS constraint? 1/10 clock period.
If my design is 100Mhz. I set the transition time as 200ps. I can get better performance because the D-FF setup time will get smaller. But,meanwhile, more buffer will add to the design. If I set the transition time as 1ns or 2ns, it will not add so much clock buffer to my design. But due to the larger transition time, the tree power consumption will be bigger! How to tradeoff the speed and power. If my target is low power!
Thanks, Jason