In planar CMOS fabrication, there is a parasitic bipolar (PNP) transistor that is formed between the drain, N-well, and substrate of a CMOS device. Under normal circumstances, this device is 'off', because the voltage due to charged particles in the N-Well region w.r.t. the substrate is too low to forward-bias this parasitic base-emitter junction. However, if enough charge builds up in the N-Well region (either because of insufficient contacts between the power supply (Vdd) rail and the NWell region, or because of an uncharacteristically high inrush of charge carriers into the region like that associated with an ESD discharge) then this vertically-oriented, parasitic transistor turns on and begins to conduct current between the drain and the substrate. With virtually no resistance across the silicided drain region, the current quickly and permanently destroys the device.
That is why most technologies will require a silicide block over the drain (and source) region - to add series resistance to the leg that is attached to the pad. This series resistance serves two purposes - one is to limit the current through the 'turned-on' parasitic transistor, and the other is because this forms something of a voltage divider which knocks down the potential that is applied to the CMOS device terminals during an ESD event.
I hope this helps.